1. Field of the Invention
This invention generally relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device to enhance the uniformity of the semiconductor device.
2. Description of Related Art
As the line width and the size of the semiconductor device become smaller, it is unavoidable that the polysilicon electrode of the MOSFET and the memory device become smaller. When the integration of the devices increases, the resistance of the source region and the drain region usually increases. However, as the size of the device shrinks and its process margin declines, the uniformity of the semiconductor devices becomes worse.
During the fabrication of the MOSFET, after the gate electrode is formed by forming a gate oxide layer and a polysilicon layer, the spacer made of silicon oxide or silicon nitride will be formed on the two sidewalls of the gate electrode. Later on, the ion implantation is performed to form the source and drain regions at the two sides of the gate electrode and then the salicide process is performed. However, if the silicon oxide spacer is employed, a cleaning step has to be performed to remove the native oxide layer and impurity on the surface of the gate electrode and the substrate before performing the salicide process. A portion of the silicon oxide spacer may be removed during the cleaning step. Hence, the subsequently formed silicide would be very close to the source/drain extension, which is easy to cause the junction leakage problems. On the other hand, if the silicon nitride spacer is employed to avoid the junction leakage problems, because the dielectric constant of silicon nitride is higher than that of silicon oxide, the silicon nitride spacer results in a larger parasitic capacitance between the gate and the source/drain region, thus deteriorating the device performance.
A composite silicon oxide/silicon nitride spacer may also be formed on the sidewalls of the gate after defining the gate electrode. The composite spacer can be formed by forming an offset oxide layer covering the substrate and the gate electrode, forming a silicon nitride layer covering the offset oxide layer and then performing anisotropic etching to remove a portion of silicon nitride layer until the offset oxide layer is exposed. The remaining offset oxide layer can protect the surface of the substrate when performing the ion implantation step to the substrate. However, when the size of the device and the line-width shrink, the thickness of each layer and the process margin in each layer also become smaller. Especially, when the thickness of the offset oxide layer is less than or about 100 Å, the thin offset oxide layer can easily be overetched and the thickness of the remaining offset oxide layer is not uniform in various locations. Since the thickness of the remaining offset oxide layer is varied, the junction depth of the source/drain region becomes non-uniform after the ion implantation step through the non-uniform offset oxide layer. In addition to the non-uniform depth of the source/drain region, the effective channel length of the gate electrode may be changed, which significantly affects the uniformity of the semiconductor devices on the wafer.